Presentation 2007-09-20
Proposal and Application of Memory with Digit-Width Converter
Yuhki YAMABE, Kazuya TANIGAWA, Tetsuo HIRONAKA,
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Abstract(in English) We research to enhance the performance of the dynamic reconfigurable processor by reducing the needs of dynamic reconfiguration by introducing digit-serial operation units. However, there is a problem that it is required to convert the bit-width, when a conventional parallel memory is used in the processor. To meet the requirements, we propose a novel memory architecture which support two data access type, parallel data access and digit-serial data access. By using this novel memory architecture, it is possible to decrease the chip area. In this paper, we present a high precise FIR filter can be compactly realized by combining digit-serial operation units and the proposed memory architecture by detail chip design.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Digit-serial / Memory / Parallel/Serial Conversion / FIR
Paper # RECONF2007-15
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Conference Information
Committee RECONF
Conference Date 2007/9/13(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Proposal and Application of Memory with Digit-Width Converter
Sub Title (in English)
Keyword(1) Digit-serial
Keyword(2) Memory
Keyword(3) Parallel/Serial Conversion
Keyword(4) FIR
1st Author's Name Yuhki YAMABE
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Kazuya TANIGAWA
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name Tetsuo HIRONAKA
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 2007-09-20
Paper # RECONF2007-15
Volume (vol) vol.107
Number (no) 225
Page pp.pp.-
#Pages 6
Date of Issue