| Presentation | 2007-09-07 CAIRN3 : An FPGA Implementation of the Sieving Step with the Lattice Sieving Takeshi SHIMOYAMA, Tetsuya IZU, Jun KOGURE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The hardness of the integer factorization problem assures the security of some public-key cryptosystems including RSA, and the number field sieve method (NFS), the most efficient algorithm for factoring large integers currently, is a threat for such cryptosystems. Recently, Izu et al. developed a dedicated sieving device CAIRN 2 with Xilinx's FPGA which is designed to handle up to 768-bit integers. However, since CAIRN 2 uses the line sieving, it is not optimized from the viewpoint of the efficiency. In this paper, we report some results of an FPGA-based sieving hardware CAIRN 3 with the lattice sieving. In the experimental sieving for a 768-bit integer (RSA768), CAIRN 3 is about 38 times faster than CAIRN 2. It is estimated that the full sieving for RSA768 requires about 270 years with single CAIRN 3. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Integer factorization / the number field sieve method (NFS) / the sieving step / implementation / FPGA |
| Paper # | ISEC2007-84 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2007/8/31(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | CAIRN3 : An FPGA Implementation of the Sieving Step with the Lattice Sieving |
| Sub Title (in English) | |
| Keyword(1) | Integer factorization |
| Keyword(2) | the number field sieve method (NFS) |
| Keyword(3) | the sieving step |
| Keyword(4) | implementation |
| Keyword(5) | FPGA |
| 1st Author's Name | Takeshi SHIMOYAMA |
| 1st Author's Affiliation | FUJITSU Limited() |
| 2nd Author's Name | Tetsuya IZU |
| 2nd Author's Affiliation | FUJITSU Limited |
| 3rd Author's Name | Jun KOGURE |
| 3rd Author's Affiliation | FUJITSU Limited |
| Date | 2007-09-07 |
| Paper # | ISEC2007-84 |
| Volume (vol) | vol.107 |
| Number (no) | 209 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |