| Presentation | 2007/7/26 A Typical-case Design Methodology Mitigating Timing Constraints and its Evaluation via Co-Simulations Yuji KUNITAKE, Akihiro CHIYONOBU, Koichiro TANAKA, Toshinori SATO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The deep submicron semiconductor technologies have increased process variations. They make worst-case designs impossible. This is because larger variations require larger design margins. In order to realize robust designs, we have to design LSIs by considering typical-cases rather than worst cases. We are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In order to evaluate the CTV, we have to consider circuit delay. We build a co-simulation environment by combining gate level simulation with architectural level simulation. We evaluate the CTV and its enhanced techniques by the co-simulation environment. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | parameter variations / co-simulation / worst-case design / typical-case design methodology / reliability |
| Paper # | DC2007-11 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2007/7/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Typical-case Design Methodology Mitigating Timing Constraints and its Evaluation via Co-Simulations |
| Sub Title (in English) | |
| Keyword(1) | parameter variations |
| Keyword(2) | co-simulation |
| Keyword(3) | worst-case design |
| Keyword(4) | typical-case design methodology |
| Keyword(5) | reliability |
| 1st Author's Name | Yuji KUNITAKE |
| 1st Author's Affiliation | Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology() |
| 2nd Author's Name | Akihiro CHIYONOBU |
| 2nd Author's Affiliation | Fujitsu Laboratories Ltd. |
| 3rd Author's Name | Koichiro TANAKA |
| 3rd Author's Affiliation | Faculty of Information Science, Kyushu Sangyo University |
| 4th Author's Name | Toshinori SATO |
| 4th Author's Affiliation | System LSI Research Center, Kyushu University |
| Date | 2007/7/26 |
| Paper # | DC2007-11 |
| Volume (vol) | vol.107 |
| Number (no) | 174 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |