Presentation | 2007/7/26 Implementation of Asynchronous Circuits on FPGA and their Evaluation Atsushi MATSUMOTO, Tomohiro YONEDA, Takahiro HANYU, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we propose the method to implement asynchronous circuits on FPGA. The circuits are generated by the automation process we proposed. This proposition consists of two topics, insertion of reconfigurable delay elements and technology mapping for performance improvement. These two techniques are essential to enhance the performance of asynchronous circuit because FPGA tools are optimized for synchronous system. Some asynchronous circuits are implemented by using the proposed method and evaluated in terms of speed and area. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Asynchronous / Reconfigurable Delay Element / Bundled data / FPGA |
Paper # | DC2007-10 |
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Committee | DC |
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Conference Date | 2007/7/26(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Implementation of Asynchronous Circuits on FPGA and their Evaluation |
Sub Title (in English) | |
Keyword(1) | Asynchronous |
Keyword(2) | Reconfigurable Delay Element |
Keyword(3) | Bundled data |
Keyword(4) | FPGA |
1st Author's Name | Atsushi MATSUMOTO |
1st Author's Affiliation | Research Institute of Electrical Communication Tohoku University() |
2nd Author's Name | Tomohiro YONEDA |
2nd Author's Affiliation | Infrastructure Systems Research Division, National Institute of Infomatics |
3rd Author's Name | Takahiro HANYU |
3rd Author's Affiliation | Research Institute of Electrical Communication Tohoku University |
Date | 2007/7/26 |
Paper # | DC2007-10 |
Volume (vol) | vol.107 |
Number (no) | 174 |
Page | pp.pp.- |
#Pages | 6 |
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