Presentation 2007-08-24
An On-Chip Noise Canceler with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
Yasumi NAKAMURA, Makoto TAKAMIYA, Takayasu SAKURAI,
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Abstract(in English) An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Noise Canceller / Power Integrity / VLSI / Power Supply / High Voltage / Decoupling / Nanosecond
Paper # SDM2007-157,ICD2007-85
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Conference Date 2007/8/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An On-Chip Noise Canceler with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
Sub Title (in English)
Keyword(1) Noise Canceller
Keyword(2) Power Integrity
Keyword(3) VLSI
Keyword(4) Power Supply
Keyword(5) High Voltage
Keyword(6) Decoupling
Keyword(7) Nanosecond
1st Author's Name Yasumi NAKAMURA
1st Author's Affiliation Center for Collaborative Research, University of Tokyo()
2nd Author's Name Makoto TAKAMIYA
2nd Author's Affiliation VLSI Design and Education Center, University of Tokyo
3rd Author's Name Takayasu SAKURAI
3rd Author's Affiliation Center for Collaborative Research, University of Tokyo
Date 2007-08-24
Paper # SDM2007-157,ICD2007-85
Volume (vol) vol.107
Number (no) 195
Page pp.pp.-
#Pages 4
Date of Issue