Presentation 2007-08-23
Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI
Satoshi Hanami, Shigeyoshi Watanabe, Manabu Kobayashi, Toshitoku Takabatake,
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Abstract(in English) Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of multi-supply-voltage and dynamic voltage scheme for product-sum operation. The reduction ratio of power dissipation of dynamic voltage scheme is larger than that of multi-supply-voltage scheme.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) system LSI / dual supply voltage scheme / dynamic current / gate leakage current / subthreshold leakage current / MOSFET / scaling rule / path-delay distribution
Paper # SDM2007-149,ICD2007-77
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Committee ICD
Conference Date 2007/8/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI
Sub Title (in English)
Keyword(1) system LSI
Keyword(2) dual supply voltage scheme
Keyword(3) dynamic current
Keyword(4) gate leakage current
Keyword(5) subthreshold leakage current
Keyword(6) MOSFET
Keyword(7) scaling rule
Keyword(8) path-delay distribution
1st Author's Name Satoshi Hanami
1st Author's Affiliation Department of Information Science, Shonan Institute of Technology()
2nd Author's Name Shigeyoshi Watanabe
2nd Author's Affiliation Department of Information Science, Shonan Institute of Technology
3rd Author's Name Manabu Kobayashi
3rd Author's Affiliation Department of Information Science, Shonan Institute of Technology
4th Author's Name Toshitoku Takabatake
4th Author's Affiliation Department of Information Science, Shonan Institute of Technology
Date 2007-08-23
Paper # SDM2007-149,ICD2007-77
Volume (vol) vol.107
Number (no) 195
Page pp.pp.-
#Pages 4
Date of Issue