| Presentation | 2007-08-23 A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms Atsufumi SHIBAYAMA, Koichi NOSE, Sunao TORII, Masayuki MIZUNO, Masato EDAHIRO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Methods for clock generation, distribution, and synchronization in system-on-chip (SOC) designs have become important issues because the number of cores in SOCs has increased and these cores require individual clocks of varying frequencies. A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-core / system-on-chip / SOC / clock / synchronization |
| Paper # | SDM2007-147,ICD2007-75 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/8/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms |
| Sub Title (in English) | |
| Keyword(1) | multi-core |
| Keyword(2) | system-on-chip |
| Keyword(3) | SOC |
| Keyword(4) | clock |
| Keyword(5) | synchronization |
| 1st Author's Name | Atsufumi SHIBAYAMA |
| 1st Author's Affiliation | System IP Core Research Laboratories, NEC() |
| 2nd Author's Name | Koichi NOSE |
| 2nd Author's Affiliation | Device Platform Research Laboratories, NEC |
| 3rd Author's Name | Sunao TORII |
| 3rd Author's Affiliation | System IP Core Research Laboratories, NEC |
| 4th Author's Name | Masayuki MIZUNO |
| 4th Author's Affiliation | Device Platform Research Laboratories, NEC |
| 5th Author's Name | Masato EDAHIRO |
| 5th Author's Affiliation | System IP Core Research Laboratories, NEC |
| Date | 2007-08-23 |
| Paper # | SDM2007-147,ICD2007-75 |
| Volume (vol) | vol.107 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |