| Presentation | 2007-08-23 Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of power supply, consumes much power; hence, we have devised a new architecture called a multiphase-output level shift system (M-LS) which has only three transistors in each LS and cuts off short current perfectly. Moreover, we have connected between the adjacent phases of M-LS with a resistor to improve phase accuracy. The two key techniques mentioned above make power consumption 1/15 of the conventional LS. The PLL consumes about 1mA at 123MHz and accomplishes 63-phase accuracy of 0.5LSB. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multiphase Clock / PLL / Level Shift System / Low Power / High Phase Accuracy |
| Paper # | SDM2007-146,ICD2007-74 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/8/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application |
| Sub Title (in English) | |
| Keyword(1) | Multiphase Clock |
| Keyword(2) | PLL |
| Keyword(3) | Level Shift System |
| Keyword(4) | Low Power |
| Keyword(5) | High Phase Accuracy |
| 1st Author's Name | Akinori Matsumoto |
| 1st Author's Affiliation | Strategic Semiconductor Development Center Matsushita Electric Industrial Co.,Ltd.() |
| 2nd Author's Name | Shiro Sakiyama |
| 2nd Author's Affiliation | Strategic Semiconductor Development Center Matsushita Electric Industrial Co.,Ltd. |
| 3rd Author's Name | Yusuke Tokunaga |
| 3rd Author's Affiliation | Strategic Semiconductor Development Center Matsushita Electric Industrial Co.,Ltd. |
| 4th Author's Name | Takashi Morie |
| 4th Author's Affiliation | Strategic Semiconductor Development Center Matsushita Electric Industrial Co.,Ltd. |
| 5th Author's Name | Shiro Dosho |
| 5th Author's Affiliation | Strategic Semiconductor Development Center Matsushita Electric Industrial Co.,Ltd. |
| Date | 2007-08-23 |
| Paper # | SDM2007-146,ICD2007-74 |
| Volume (vol) | vol.107 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |