Presentation 2007-08-23
Design Trends of High Performance PLLs and DLLs
Shiro Dosho,
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Abstract(in English) Along with the development of the mobile terminals and system LSIs, Phase Locked Loops(PLL) and Delay Locked Loops(DLL) are one of the most improved circuits in the last few decades. In addition, the technique to predict the phase noise has been improved drastically to the level that the simulated jitter characteristics are very close to that of real circuits. In this paper, the recent design trends of high performances PLLs and DLLs and the simulation method of the phase noise are described, the techniques of high performance loop filters, adaptive biasing, fractional-N synthesizer and so on.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Phase Locked Loops / Delay Locked Loops / Loop Filter / Adaptive Biasing / Fractional Divider
Paper # SDM2007-145,ICD2007-73
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Committee ICD
Conference Date 2007/8/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design Trends of High Performance PLLs and DLLs
Sub Title (in English)
Keyword(1) Phase Locked Loops
Keyword(2) Delay Locked Loops
Keyword(3) Loop Filter
Keyword(4) Adaptive Biasing
Keyword(5) Fractional Divider
1st Author's Name Shiro Dosho
1st Author's Affiliation Matsushita Electric Industrial Co. Ltd. Strategic Semiconductor Development Center()
Date 2007-08-23
Paper # SDM2007-145,ICD2007-73
Volume (vol) vol.107
Number (no) 195
Page pp.pp.-
#Pages 6
Date of Issue