| Presentation | 2007-08-23 Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding Hiroaki SHIKANO, Masaki ITO, Takashi TODAKA, Takanobu TSUNODA, Tomoyuki KODAMA, Masafumi ONOUCHI, Kunio UCHIYAMA, Toshihiko ODAKA, Tatsuya KAMEI, Ei NAGAHAMA, Manabu KUSAOKE, Yusuke NITTA, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption for SoCs of embedded systems. Memory architecture of CPUs and ACCs were unified to improve programming and compiling efficiency. For preliminary evaluation of the HMCP architecture, AAC-LC stereo audio encoding is parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamic reconfigurable processor (DRP) accelerator cores. The performance evaluation shows that 54x AAC encoding is achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which realizes encoding of a whole CD in 1-2 minutes. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Heterogeneous multi-core / parallel processing / accelerator / dynamic reconfigurable processor / AAC encoding |
| Paper # | SDM2007-143,ICD2007-71 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/8/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding |
| Sub Title (in English) | |
| Keyword(1) | Heterogeneous multi-core |
| Keyword(2) | parallel processing |
| Keyword(3) | accelerator |
| Keyword(4) | dynamic reconfigurable processor |
| Keyword(5) | AAC encoding |
| 1st Author's Name | Hiroaki SHIKANO |
| 1st Author's Affiliation | Hitachi, Ltd. : Dept. of Computer Science, Waseda University() |
| 2nd Author's Name | Masaki ITO |
| 2nd Author's Affiliation | Hitachi, Ltd. |
| 3rd Author's Name | Takashi TODAKA |
| 3rd Author's Affiliation | Hitachi, Ltd. |
| 4th Author's Name | Takanobu TSUNODA |
| 4th Author's Affiliation | Hitachi, Ltd. |
| 5th Author's Name | Tomoyuki KODAMA |
| 5th Author's Affiliation | Hitachi, Ltd. |
| 6th Author's Name | Masafumi ONOUCHI |
| 6th Author's Affiliation | Hitachi, Ltd. |
| 7th Author's Name | Kunio UCHIYAMA |
| 7th Author's Affiliation | Hitachi, Ltd. : Dept. of Computer Science, Waseda University |
| 8th Author's Name | Toshihiko ODAKA |
| 8th Author's Affiliation | Hitachi, Ltd. : Dept. of Computer Science, Waseda University |
| 9th Author's Name | Tatsuya KAMEI |
| 9th Author's Affiliation | Renesas Technology Corporation |
| 10th Author's Name | Ei NAGAHAMA |
| 10th Author's Affiliation | Renesas Technology Corporation |
| 11th Author's Name | Manabu KUSAOKE |
| 11th Author's Affiliation | Renesas Technology Corporation |
| 12th Author's Name | Yusuke NITTA |
| 12th Author's Affiliation | Renesas Technology Corporation |
| 13th Author's Name | Yasutaka WADA |
| 13th Author's Affiliation | Dept. of Computer Science, Waseda University |
| 14th Author's Name | Keiji KIMURA |
| 14th Author's Affiliation | Dept. of Computer Science, Waseda University |
| 15th Author's Name | Hironori KASAHARA |
| 15th Author's Affiliation | Dept. of Computer Science, Waseda University |
| Date | 2007-08-23 |
| Paper # | SDM2007-143,ICD2007-71 |
| Volume (vol) | vol.107 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |