Presentation 2007-08-23
Homogenous Dual-Processor Core with Shared L1 Cache for Mobile Multimedia SoC
Tetsu HOSOKI, Takao YAMAMOTO, Masayuki YAMASAKI, Keisuke KANEKO, Masaitsu NAKAJIMA,
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Abstract(in English) We propose a novel dual-processor core which adopts a shared L1 cache with active way scheme [1]. In this scheme, each way of cache is owned by specific thread or processor and replace operation is only happened to its own ways. By implementing 2 stages cache access with this scheme, this structure only requires dual port TAG, and no dual port DATA memory to realize simultaneous access from both processors. This architecture can guarantee no cache thrashing and no snoop overhead. And also by sharing cache memory and cache controller, power dissipation is 23% smaller in case of heavy load and area is 29% smaller than dual processor core with snoop cache.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Homogeneous / Dual-processor / Snoop cache / Shared cache / Low power
Paper # SDM2007-142,ICD2007-70
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Committee ICD
Conference Date 2007/8/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Homogenous Dual-Processor Core with Shared L1 Cache for Mobile Multimedia SoC
Sub Title (in English)
Keyword(1) Homogeneous
Keyword(2) Dual-processor
Keyword(3) Snoop cache
Keyword(4) Shared cache
Keyword(5) Low power
1st Author's Name Tetsu HOSOKI
1st Author's Affiliation Strategic Semiconductor Development Center, Matsushita Electric Industrial Co.,Ltd.()
2nd Author's Name Takao YAMAMOTO
2nd Author's Affiliation Strategic Semiconductor Development Center, Matsushita Electric Industrial Co.,Ltd.
3rd Author's Name Masayuki YAMASAKI
3rd Author's Affiliation Strategic Semiconductor Development Center, Matsushita Electric Industrial Co.,Ltd.
4th Author's Name Keisuke KANEKO
4th Author's Affiliation Strategic Semiconductor Development Center, Matsushita Electric Industrial Co.,Ltd.
5th Author's Name Masaitsu NAKAJIMA
5th Author's Affiliation Strategic Semiconductor Development Center, Matsushita Electric Industrial Co.,Ltd.
Date 2007-08-23
Paper # SDM2007-142,ICD2007-70
Volume (vol) vol.107
Number (no) 195
Page pp.pp.-
#Pages 5
Date of Issue