| Presentation | 2007-08-23 Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors Masami NAKAJIMA, Koichi ISHIMI, Hayato FUJIWARA, Kazuya ISHIDA, Naoto OKUMURA, Norio MASUI, Hiroyuki KONDO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 Matrix processors reduced 45% power consumption. The performance-oriented multi-bank Matrix processor with 2-read-1 -write calculation and background I/O operation is adopted. The 1GHz CPU is realized by the delay management network applied for any kinds of applications and process technologies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multi-core SoC / Configurable Heterogeneous Architecture / Matrix Processor / Delay Management Network |
| Paper # | SDM2007-141,ICD2007-69 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/8/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors |
| Sub Title (in English) | |
| Keyword(1) | Multi-core SoC |
| Keyword(2) | Configurable Heterogeneous Architecture |
| Keyword(3) | Matrix Processor |
| Keyword(4) | Delay Management Network |
| 1st Author's Name | Masami NAKAJIMA |
| 1st Author's Affiliation | System Core Technology Div., Renesas Technology Corp.() |
| 2nd Author's Name | Koichi ISHIMI |
| 2nd Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 3rd Author's Name | Hayato FUJIWARA |
| 3rd Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 4th Author's Name | Kazuya ISHIDA |
| 4th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 5th Author's Name | Naoto OKUMURA |
| 5th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 6th Author's Name | Norio MASUI |
| 6th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 7th Author's Name | Hiroyuki KONDO |
| 7th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| Date | 2007-08-23 |
| Paper # | SDM2007-141,ICD2007-69 |
| Volume (vol) | vol.107 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |