Presentation 2007-07-20
Hardware Implementations of the 128-bit Blockcipher CLEFIA
Taizo SHIRAI, Kyoji SHIBUTANI, Toru AKISHITA, Shiho MORIAI, Tetsu IWATA,
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Abstract(in English) This paper presents optimization techniques and evaluation results in hardware implementations of the 128-bit blockcipher CLEFIA. We investigated efficient implementaions of two S-boxes and two diffusion matrices in F-functions, and the DoubleSwap function used in the key scheduling part. Using a 0.09μm CMOS ASIC library, our fast implementation and compact implementation of CLEFIA with 128-bit keys achieve 1.60 Gbps with less than 6 Kgate and 0.71 Gbps with less than 5 Kgate, respectively. These figures are so advantageous to the best known results of hardware performance of AES and Camellia that CLEFIA is a highly efficient blockcipher in hardware implementations.
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Keyword(in English) blockcipher / CLEFIA / hardware implementation
Paper # ISEC2007-49
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Committee ISEC
Conference Date 2007/7/13(1days)
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Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware Implementations of the 128-bit Blockcipher CLEFIA
Sub Title (in English)
Keyword(1) blockcipher
Keyword(2) CLEFIA
Keyword(3) hardware implementation
1st Author's Name Taizo SHIRAI
1st Author's Affiliation Sony Corporation()
2nd Author's Name Kyoji SHIBUTANI
2nd Author's Affiliation Sony Corporation
3rd Author's Name Toru AKISHITA
3rd Author's Affiliation Sony Corporation
4th Author's Name Shiho MORIAI
4th Author's Affiliation Sony Corporation
5th Author's Name Tetsu IWATA
5th Author's Affiliation Nagoya University
Date 2007-07-20
Paper # ISEC2007-49
Volume (vol) vol.107
Number (no) 141
Page pp.pp.-
#Pages 8
Date of Issue