| Presentation | 2007-07-27 Investigation of Parasitic Capacitance to Improve EMC Macro Model LECCS around 1GHz A. TAKAHASHI, K. IOKIBE, U. Paoletti, O. WADA, Y. TOYOTA, R. KOGA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | High frequency currents flowing in power supply networks of an IC/LSI has been estimated by an EMC macro model. The high frequency currents due to the simultaneous switching noise of IC/LSI involving large amount of CMOS transistor is modeled with a linear equivalent circuit and current sources. The linear equivalent circuit decreased its accuracy in impedance due to parasitic capacitances causing anti-resonances in the power supply networks. This paper shows with results of experimental and numerical analysis that the parasitic capacitances on the package and printed circuit board cause the anti-resonance. The power supply network impedance were obtained experimentally by use of three evaluation boards with different parasitic capacitances. The parasitic capacitances of the boards were calculated numerically by high-frequency electromagnetic analysis software Sonnet. Impedance simulations by considering the parasitic capacitance shows that an appropriate connection of parasitic capacitances to the LECCS model can expand an available frequency range of the model beyond 1 GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Electromagnetic compatibility / Power network impedance / CMOS IC / LECCS model / Parasitic capacitance / Sonnet |
| Paper # | EMCJ2007-33,EMD2007-19 |
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| Conference Information | |
| Committee | EMD |
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| Conference Date | 2007/7/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electromechanical Devices (EMD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Investigation of Parasitic Capacitance to Improve EMC Macro Model LECCS around 1GHz |
| Sub Title (in English) | |
| Keyword(1) | Electromagnetic compatibility |
| Keyword(2) | Power network impedance |
| Keyword(3) | CMOS IC |
| Keyword(4) | LECCS model |
| Keyword(5) | Parasitic capacitance |
| Keyword(6) | Sonnet |
| 1st Author's Name | A. TAKAHASHI |
| 1st Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University() |
| 2nd Author's Name | K. IOKIBE |
| 2nd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| 3rd Author's Name | U. Paoletti |
| 3rd Author's Affiliation | Graduate School of Engineering, Kyoto University |
| 4th Author's Name | O. WADA |
| 4th Author's Affiliation | Graduate School of Engineering, Kyoto University |
| 5th Author's Name | Y. TOYOTA |
| 5th Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| 6th Author's Name | R. KOGA |
| 6th Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| Date | 2007-07-27 |
| Paper # | EMCJ2007-33,EMD2007-19 |
| Volume (vol) | vol.107 |
| Number (no) | 168 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |