Presentation 2007-07-27
Fabrication and characterization of Self-planarized Bi_2Sr_2CaCu_2O_x intrinsic Josephson junctions by acid-treated process
T. Kato, K. Someya, T. Yoshida, H. Nawa, T. Mouri, H. Tominaga, Y. Irie, K. Hamasaki, H. Shimakage,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have previously reported on the fabrication technique using acid-treated process, and also analyzed the I-V characteristics (I_c-T, I_r-T) of the self-planarized Bi-2212 intrinsic Josephson junctions. In this process, the thickness of self-planarizing layer (insulator) is the same as the stack height (<40nm), which is decided by soaking time into a dilute acid solution. Because of the ultra thin insulating layer (self planarized layer, <40nm), microshorts might occur at the edge of the crystal (typical size: 1×1mm^2), and in the insulating layer between the wiring layer (counter electrode) and Bi-2212 crystal (base electrode). In this study, to avoid the microshorts we modified the process. The crystal except for the stack was perfectly varied to insulating material by soaking it into the dilute hydrochloric acid (pH~1.4) for about 20 minutes. By using this process, we reproducibility fabricated the stacks with large hysteresis at 77K.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Intrinsic Josephson junction / acid-treated process / self-planarizing-method
Paper # SCE2007-13
Date of Issue

Conference Information
Committee SCE
Conference Date 2007/7/20(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fabrication and characterization of Self-planarized Bi_2Sr_2CaCu_2O_x intrinsic Josephson junctions by acid-treated process
Sub Title (in English)
Keyword(1) Intrinsic Josephson junction
Keyword(2) acid-treated process
Keyword(3) self-planarizing-method
1st Author's Name T. Kato
1st Author's Affiliation Nagaoka University of Technology()
2nd Author's Name K. Someya
2nd Author's Affiliation Nagaoka University of Technology
3rd Author's Name T. Yoshida
3rd Author's Affiliation Nagaoka University of Technology
4th Author's Name H. Nawa
4th Author's Affiliation Nagaoka University of Technology
5th Author's Name T. Mouri
5th Author's Affiliation Nagaoka University of Technology
6th Author's Name H. Tominaga
6th Author's Affiliation Nagaoka University of Technology
7th Author's Name Y. Irie
7th Author's Affiliation Nagaoka University of Technology
8th Author's Name K. Hamasaki
8th Author's Affiliation Nagaoka University of Technology
9th Author's Name H. Shimakage
9th Author's Affiliation KARC, National Institute of Information and Communications Technology
Date 2007-07-27
Paper # SCE2007-13
Volume (vol) vol.107
Number (no) 171
Page pp.pp.-
#Pages 5
Date of Issue