Presentation 2007-06-29
Investigation of Operation Tolerance of a Semiconductor Integrated Optical Digital-to-Analog Converter
Kengo SAWADA, Hiroyuki UENOHARA,
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Abstract(in English) To realize an optical packet switch operating with high speed and low power consumption, we have investigated an optical digital-to-analog converter (ODAC) type label processor. It converts serial bits of label into a single pulse with multi-level amplitude. So multiple label signals can be recognized by one step process, and reduction of power consumption and the number of optical devices can be expected. Moreover, the integration of the ODAC on semiconductors is important for downsizing. We have reported 2-bit digital-to-analog conversion with a semiconductor integrated ODAC. However, output power fluctuation with phase difference, frequency chirping and extinction ratio are technical issues. In this report, we estimate the influence of chirping in a semiconductor ODAC which causes output power fluctuation, and analyze the operation tolerance of phase, chirping, intensity, and extinction ratio of an ODAC by calculating the BER of output signal. The results indicate the operable conditions of label recognition with the semiconductor ODAC.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Optical Packet Switch / Optical digital-to-analog converter (ODAC) / Semiconductor integration
Paper # OPE2007-28,LQE2007-29
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Conference Information
Committee LQE
Conference Date 2007/6/22(1days)
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Registration To Lasers and Quantum Electronics (LQE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Investigation of Operation Tolerance of a Semiconductor Integrated Optical Digital-to-Analog Converter
Sub Title (in English)
Keyword(1) Optical Packet Switch
Keyword(2) Optical digital-to-analog converter (ODAC)
Keyword(3) Semiconductor integration
1st Author's Name Kengo SAWADA
1st Author's Affiliation Microsystem Research Center, P&I Lab., Tokyo Institute of Technology()
2nd Author's Name Hiroyuki UENOHARA
2nd Author's Affiliation Microsystem Research Center, P&I Lab., Tokyo Institute of Technology
Date 2007-06-29
Paper # OPE2007-28,LQE2007-29
Volume (vol) vol.107
Number (no) 125
Page pp.pp.-
#Pages 6
Date of Issue