Presentation 2007/6/18
Low Switching Loss Power MOSFET with Dual Gate Structure
Chien-Nan Liao, Feng-Tso Chien, Yao-Tsung. Tsai,
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Abstract(in English) Low gate charge power vertical double-diffused MOSFET devices are required for high frequency circuit system. In this study, we proposed a power MOSFET structure with a dual gate structure which realizes the small gate charge without significantly degrading breakdown voltage. The dual gate eliminates partial gate area which effects switching speed and switching loss strongly. The dual gate structure features the formation of removed gate area portion combining with the additional np-region at the surface of the n drift layer. Reduction of the gate charge results in an improvement of switching performance. The gate charge and the figure of merit of the dual gate with np-region cell structure are reduced 49% and 33% compared with those of the conventional cell, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Power MOSFET / VDMOSFET / gate charge / Switching Loss
Paper # ED2007-123,SDM2007-128
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Committee ED
Conference Date 2007/6/18(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Low Switching Loss Power MOSFET with Dual Gate Structure
Sub Title (in English)
Keyword(1) Power MOSFET
Keyword(2) VDMOSFET
Keyword(3) gate charge
Keyword(4) Switching Loss
1st Author's Name Chien-Nan Liao
1st Author's Affiliation Department of Electrical Engineering, National Central University()
2nd Author's Name Feng-Tso Chien
2nd Author's Affiliation Department of Electronic Engineering, Feng Chia University
3rd Author's Name Yao-Tsung. Tsai
3rd Author's Affiliation Department of Electrical Engineering, National Central University
Date 2007/6/18
Paper # ED2007-123,SDM2007-128
Volume (vol) vol.107
Number (no) 110
Page pp.pp.-
#Pages 4
Date of Issue