Presentation 2007/6/18
Establishing Read Operation Bias Schemes for 3-D Pillar-Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Seongjae CHO, Il Han PARK, Jung Hoon LEE, Jang-Gn YUN, Doo-Hyun KIM, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK,
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Abstract(in English) Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Memory Array / electrical interference / 3-D memory device / read operation / PCI (paired cell interference)
Paper # ED2007-108,SDM2007-113
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Committee ED
Conference Date 2007/6/18(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Establishing Read Operation Bias Schemes for 3-D Pillar-Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Sub Title (in English)
Keyword(1) Memory Array
Keyword(2) electrical interference
Keyword(3) 3-D memory device
Keyword(4) read operation
Keyword(5) PCI (paired cell interference)
1st Author's Name Seongjae CHO
1st Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University()
2nd Author's Name Il Han PARK
2nd Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
3rd Author's Name Jung Hoon LEE
3rd Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
4th Author's Name Jang-Gn YUN
4th Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
5th Author's Name Doo-Hyun KIM
5th Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
6th Author's Name Jong Duk LEE
6th Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
7th Author's Name Hyungcheol SHIN
7th Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
8th Author's Name Byung-Gook PARK
8th Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
Date 2007/6/18
Paper # ED2007-108,SDM2007-113
Volume (vol) vol.107
Number (no) 110
Page pp.pp.-
#Pages 4
Date of Issue