Presentation 2007/6/18
DMOS-based avalanche-mode Power-Rail ESD Clamp for a 0.35μm BCD Process
Jae-Young PARK, Dong-Jun KIM, Sang-Gyu PARK,
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Abstract(in English) A DMOS-based ESD power-rail clamp is proposed. The operation region of the proposed power-rail clamp is limited to below the onset of the snapback to avoid the danger of latch-up. The total blocking voltage of this new design can be adjusted by changing the width (or number of fingers) of the devices. From the measurement on the devices fabricated using a 0.35μm BCD Process (60V), it was observed that the proposed ESD power-rail clamp can provide 400% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven DMOS.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ESD / power-rail clamp / latch-up / DMOS-based
Paper # ED2007-98,SDM2007-103
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Committee ED
Conference Date 2007/6/18(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) DMOS-based avalanche-mode Power-Rail ESD Clamp for a 0.35μm BCD Process
Sub Title (in English)
Keyword(1) ESD
Keyword(2) power-rail clamp
Keyword(3) latch-up
Keyword(4) DMOS-based
1st Author's Name Jae-Young PARK
1st Author's Affiliation Div. of Electrical and Computer Engineering, Hanyang University()
2nd Author's Name Dong-Jun KIM
2nd Author's Affiliation Div. of Electrical and Computer Engineering, Hanyang University
3rd Author's Name Sang-Gyu PARK
3rd Author's Affiliation Div. of Electrical and Computer Engineering, Hanyang University
Date 2007/6/18
Paper # ED2007-98,SDM2007-103
Volume (vol) vol.107
Number (no) 110
Page pp.pp.-
#Pages 4
Date of Issue