Presentation 2007/6/18
Investigation of wafer warpage resulted from deep trench isolation in multi-layered SOI
Jinwoo JEONG, Hyeon Cheol KIM, Kukjin CHUN,
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Abstract(in English) In this paper, the wafer warpage that originated from the stress of DTI(deep trench isolation) is investigated. The wafer warpage resulted from oxide filled DTI with 4μm width and 40μm depth is simulated and measured. The DTI using mixed layer of 1μm thermal oxide and 0.8μm poly silicon is also considered. The wafer warpages from the room temperature to 500℃ are measured and analyzed. It is verified that the main source of the wafer warpage is the thermal stress. The wafer warpages of these DTIs at the room temperature are simulated and compared with the measured values. The difference between two values is less than 5%.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Multi-layered SOI / Wafer Warpage / Deep Trench Isolation / Thermal Stress
Paper # ED2007-85,SDM2007-90
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Committee ED
Conference Date 2007/6/18(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Investigation of wafer warpage resulted from deep trench isolation in multi-layered SOI
Sub Title (in English)
Keyword(1) Multi-layered SOI
Keyword(2) Wafer Warpage
Keyword(3) Deep Trench Isolation
Keyword(4) Thermal Stress
1st Author's Name Jinwoo JEONG
1st Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University()
2nd Author's Name Hyeon Cheol KIM
2nd Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
3rd Author's Name Kukjin CHUN
3rd Author's Affiliation School of Electrical Engineering and Computer Science, Seoul National University
Date 2007/6/18
Paper # ED2007-85,SDM2007-90
Volume (vol) vol.107
Number (no) 110
Page pp.pp.-
#Pages 4
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