Presentation 2007/6/18
CMOS Low-Noise Amplifier with Noise Suppression Technique from Gate Resistance
Ickhyun Song, Min Suk Koo, Hee Sauk Jhon, Hyungcheol Shin,
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Abstract(in English) In this paper, design and results of a fully integrated 5.8 GHz low noise amplifier (LNA) using 0.13-μm CMOS technology are presented. Commonly adopted inductive source degeneration for input impedance matching is eliminated for smaller chip area while providing reasonable input 50 Ohm matching. With a simple LC-tank structure, the effective inductance of the gate inductor was increased and its size was reduced. Also by adding capacitance between gate and source of the input transistor, a noise source from the gate resistance is partly suppressed. The layout of the LNA occupies total area of 0.7-mm^2 and the results show forward power gain (S_<21>) of 12-dB and noise figure of 3.9-dB while consuming 6.8-mW from a 1.2-V DC supply.
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Keyword(in English) CMOS / Low-noise amplifier (LNA) / Gate resistance / Noise
Paper # ED2007-53,SDM2007-58
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Committee ED
Conference Date 2007/6/18(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
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Title (in English) CMOS Low-Noise Amplifier with Noise Suppression Technique from Gate Resistance
Sub Title (in English)
Keyword(1) CMOS
Keyword(2) Low-noise amplifier (LNA)
Keyword(3) Gate resistance
Keyword(4) Noise
1st Author's Name Ickhyun Song
1st Author's Affiliation Dept. of EECS, Seoul National University()
2nd Author's Name Min Suk Koo
2nd Author's Affiliation Dept. of EECS, Seoul National University
3rd Author's Name Hee Sauk Jhon
3rd Author's Affiliation Dept. of EECS, Seoul National University
4th Author's Name Hyungcheol Shin
4th Author's Affiliation Dept. of EECS, Seoul National University
Date 2007/6/18
Paper # ED2007-53,SDM2007-58
Volume (vol) vol.107
Number (no) 110
Page pp.pp.-
#Pages 4
Date of Issue