Presentation 2007/6/18
Low Cost CMOS LNA Design Using Thin-Metal CMOS Process
Hee-Sauk Jhon, Ickhyun Song, Yeo-nam Yoon, Hyungcheol Shin,
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Abstract(in English) This paper presents the design and measurement results of cost-effective CMOS Low Noise Amplifier (LNA) for high frequency application. For low cost design, this circuit has been fabricated with a 0.18μm thin metal CMOS process which the top metal thickness is only 0.84μm. To obtain the high-quality factor inductor in LNA design, patterned-ground shields (PGS) are placed. Moreover, to eliminate additional noise source from the substrate resistive components of RF interconnects, MIM capacitor, RF-pad and grounded metal-1 were placed underneath them. The LNA achieves power gain of 15.6dB, noise figure of 3.5dB at 2.8GHz at 6.88mW power dissipation for a 1.6V power supply. It occupies a whole circuit area of 1.2mm^2.
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Keyword(in English) Low Noise Amplifier (LNA) / Thin-Metal / CMOS / Low cost
Paper # ED2007-51,SDM2007-56
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Committee ED
Conference Date 2007/6/18(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Low Cost CMOS LNA Design Using Thin-Metal CMOS Process
Sub Title (in English)
Keyword(1) Low Noise Amplifier (LNA)
Keyword(2) Thin-Metal
Keyword(3) CMOS
Keyword(4) Low cost
1st Author's Name Hee-Sauk Jhon
1st Author's Affiliation Dept. of Electrical Engineering and Computer Science, Seoul National University()
2nd Author's Name Ickhyun Song
2nd Author's Affiliation Dept. of Electrical Engineering and Computer Science, Seoul National University
3rd Author's Name Yeo-nam Yoon
3rd Author's Affiliation Dept. of Electrical Engineering and Computer Science, Seoul National University
4th Author's Name Hyungcheol Shin
4th Author's Affiliation Dept. of Electrical Engineering and Computer Science, Seoul National University
Date 2007/6/18
Paper # ED2007-51,SDM2007-56
Volume (vol) vol.107
Number (no) 110
Page pp.pp.-
#Pages 4
Date of Issue