Presentation 2007/6/8
An Embedded Programmable Logic Matrix (ePLX) and its Applications for Network Security
Mitsutaka Matsumoto, Kouta Ishibashi, Shun Kimura, Shogo Oyama, Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto, Tomonori Izumi, Takeshi Fujino,
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Abstract(in English) Low Cost Network Appliance with low power microprocessor must be connected with networks in order to realize ubiquitous network. Network security have to be considered for these appliances. The encryption processing and string matching are heavy transaction for the microprocessors, which is used low-cost, low-power Appliances. Hence, data transmission speeds is greatly decreased because of the low-performance in software processing. In order to improve device performance, we propose ePLX (embedded Programmable Logic matriX) adapted for network security transactions. In this paper, we explain the ePLX architecture and network application examples, which are installation and evaluation of DES encryption circuit, and approach to realize string matching for Intrusion Detect System (IDS).
Keyword(in Japanese) (See Japanese page)
Keyword(in English) programmable device / DES encryption circuit / string matching
Paper # SIS2007-14
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Conference Date 2007/6/8(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Embedded Programmable Logic Matrix (ePLX) and its Applications for Network Security
Sub Title (in English)
Keyword(1) programmable device
Keyword(2) DES encryption circuit
Keyword(3) string matching
1st Author's Name Mitsutaka Matsumoto
1st Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University()
2nd Author's Name Kouta Ishibashi
2nd Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
3rd Author's Name Shun Kimura
3rd Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
4th Author's Name Shogo Oyama
4th Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
5th Author's Name Hirofumi Nakano
5th Author's Affiliation Renesas Technology Corp.
6th Author's Name Takenobu Iwao
6th Author's Affiliation Renesas Technology Corp.
7th Author's Name Yoshihiro Okuno
7th Author's Affiliation Renesas Technology Corp.
8th Author's Name Kazutami Arimoto
8th Author's Affiliation Renesas Technology Corp.
9th Author's Name Tomonori Izumi
9th Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
10th Author's Name Takeshi Fujino
10th Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
Date 2007/6/8
Paper # SIS2007-14
Volume (vol) vol.107
Number (no) 94
Page pp.pp.-
#Pages 6
Date of Issue