| Presentation | 2007/6/7 The overview of the massively parallel processor based on the matrix architecture and the considerations of the image processing applications Hiroyuki YAMASAKI, Hideyuki NODA, Tetsu NISHIJIMA, Kanako YOSHIDA, Takayuki GYOTEN, Tetsushi TANIZAKI, Katsuya MIZUMOTO, Masami NAKAJIMA, Yoshihiro OKUNO, Kazutami ARIMOTO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, the installed applications in the digital devices has been remarkably progressed. Considering these backgrounds, we have developed the massively parallel processor based on the matrix architecture which realizes both high flexibilities and high performance ability while achieving small silicon area and low power consumption, which is attractive solution for Today's SoCs. This paper introduces the overview of the hardware architecture and the software development environment of this processor, and reports the results of the image processing applications. The evaluated performance of applying to 3x3 convolution filter processing is 147-times and 280-times higher than the conventional 32bit RISC CPUs for 16bit and 8bit data accuracy, respectively. The proposed processor is expected to have over 100-times higher performance than the conventional CPUs for various algorithms comparatively suitable for parallel processing, therefore, it offers promising possibilities to the software solutions realized in SoCs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | massively parallel processing / SIMD / processor / image processing |
| Paper # | SIS2007-4 |
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| Committee | SIS |
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| Conference Date | 2007/6/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Smart Info-Media Systems (SIS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The overview of the massively parallel processor based on the matrix architecture and the considerations of the image processing applications |
| Sub Title (in English) | |
| Keyword(1) | massively parallel processing |
| Keyword(2) | SIMD |
| Keyword(3) | processor |
| Keyword(4) | image processing |
| 1st Author's Name | Hiroyuki YAMASAKI |
| 1st Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp.() |
| 2nd Author's Name | Hideyuki NODA |
| 2nd Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 3rd Author's Name | Tetsu NISHIJIMA |
| 3rd Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 4th Author's Name | Kanako YOSHIDA |
| 4th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 5th Author's Name | Takayuki GYOTEN |
| 5th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 6th Author's Name | Tetsushi TANIZAKI |
| 6th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 7th Author's Name | Katsuya MIZUMOTO |
| 7th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 8th Author's Name | Masami NAKAJIMA |
| 8th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 9th Author's Name | Yoshihiro OKUNO |
| 9th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| 10th Author's Name | Kazutami ARIMOTO |
| 10th Author's Affiliation | System Solution Business Group, System Core Technology Div., Renesas Technology Corp. |
| Date | 2007/6/7 |
| Paper # | SIS2007-4 |
| Volume (vol) | vol.107 |
| Number (no) | 93 |
| Page | pp.pp.- |
| #Pages | 6 |
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