講演名 | 2007/6/18 3-Dimensional Vertically Integrated Nano-Shell All-Around-Gate MOSFET , |
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抄録(和) | |
抄録(英) | This paper reports a novel 3-dimensional vertical nano-shell all-around-gate MOSFET for ultimate device scaling. The vertical nano-shell structure can be realized by introduction of a silicon thin-body formed by chemical vapor deposition (CVD) of poly-silicon and subsequent solid phase crystallization (SPC) as well as incorporation of an electrically independent inner-gate. It was verified that the vertical nano-shell MOSFET offers immunity to short-channel effects through a comparison of device performances between a nano-shell structure (double all-around-gate) and a nano-wire structure (single all-around-gate) with the aid of a SILVACO[○!R] 3-D simulator. With diverse modulations of the bias from the independently operated inner gate, the electrical characteristics of the MOSFET and the feasibility of application to a low-power transistor are investigated. |
キーワード(和) | |
キーワード(英) | Nano-shell structure / All-around-gate / Solid phase crystallization (SPC) / Short-channel effect (SCE) |
資料番号 | ED2007-61,SDM2007-66 |
発行日 |
研究会情報 | |
研究会 | SDM |
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開催期間 | 2007/6/18(から1日開催) |
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委員長氏名(和) | |
委員長氏名(英) | |
副委員長氏名(和) | |
副委員長氏名(英) | |
幹事氏名(和) | |
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幹事補佐氏名(和) | |
幹事補佐氏名(英) |
講演論文情報詳細 | |
申込み研究会 | Silicon Device and Materials (SDM) |
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本文の言語 | ENG |
タイトル(和) | |
サブタイトル(和) | |
タイトル(英) | 3-Dimensional Vertically Integrated Nano-Shell All-Around-Gate MOSFET |
サブタイトル(和) | |
キーワード(1)(和/英) | / Nano-shell structure |
第 1 著者 氏名(和/英) | / Chung-Jin Kim |
第 1 著者 所属(和/英) | School of Electrical Engineering & Computer Science, Korea Advanced Institute of Science and Technology |
発表年月日 | 2007/6/18 |
資料番号 | ED2007-61,SDM2007-66 |
巻番号(vol) | vol.107 |
号番号(no) | 111 |
ページ範囲 | pp.- |
ページ数 | 4 |
発行日 |