| Presentation | 2007-06-01 Design of a Highly Parallel VLSI Processor Based on Functional-Unit-Level Packet Data Transfer Scheme Yoshichika FUJIOKA, Nobuhiro TOMABECHI, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Until now, network on chip technology based on course grain packet data transfer was proposed. In this paper, fine grain packet data transfer scheme is introduced to make intra-chip data transfer flexible and programmable in micronetwork. A protocol based on hybrid utilization of autonomous packed data transfer and offline scheduling/allocation is effectively employed for making a router as simple as possible, so that packed collision in the micronetwork does not occur. Because the timing control of packet-receive is automatically done in the router, complexity of VLIW control can be greatly reduced. A special control module to control the packet-send timing is proposed to realize effective packet data transfer. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network-on-chip / Parallel VLSI Processor / Semi-Autonomous Packet Routing / Reduction of Control Complexity |
| Paper # | ICD2007-34 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/5/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a Highly Parallel VLSI Processor Based on Functional-Unit-Level Packet Data Transfer Scheme |
| Sub Title (in English) | |
| Keyword(1) | Network-on-chip |
| Keyword(2) | Parallel VLSI Processor |
| Keyword(3) | Semi-Autonomous Packet Routing |
| Keyword(4) | Reduction of Control Complexity |
| 1st Author's Name | Yoshichika FUJIOKA |
| 1st Author's Affiliation | Faculty of Engineering, Hachinohe Institute of Technology() |
| 2nd Author's Name | Nobuhiro TOMABECHI |
| 2nd Author's Affiliation | Faculty of Engineering, Hachinohe Institute of Technology |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2007-06-01 |
| Paper # | ICD2007-34 |
| Volume (vol) | vol.107 |
| Number (no) | 76 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |