Presentation 2007-06-01
Architecture of the Highly Parallel Array Processor IMAPCAR and its Technology Perspective
Shorin KYO,
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Abstract(in English) Media information processing such as image compression and recognition are demending increasingly high computational performance nowadays, while still require to be low power for maintaining mobility and high reliability, and as well to provide high flexibility for reducing the development and maintainance effort of its applications. To balance these trading-off items (performance, power, and flexibility), many-core multiprocessor is becoming one promising processor architecture choice. In this paper, the author briefly described the total design strategy of IMAPCAR, a highly parallel SIMD processor integrating 128 of 4-Way VLIW cores for image recognition applications, and as well its technology perspective toward widening its application fields.
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Keyword(in English) SIMD processor / Image recognition / Many-core / Memory access pattern / Parallel algorithm
Paper # ICD2007-33
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Conference Date 2007/5/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Architecture of the Highly Parallel Array Processor IMAPCAR and its Technology Perspective
Sub Title (in English)
Keyword(1) SIMD processor
Keyword(2) Image recognition
Keyword(3) Many-core
Keyword(4) Memory access pattern
Keyword(5) Parallel algorithm
1st Author's Name Shorin KYO
1st Author's Affiliation System IP Core Research Laboratories, NEC Corporation()
Date 2007-06-01
Paper # ICD2007-33
Volume (vol) vol.107
Number (no) 76
Page pp.pp.-
#Pages 6
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