Presentation 2007-06-01
The Dynamic Instruction Scheduler for ALU Cascading
Kosuke OGATA, Jun YAO, Shinobu MIWA, Hajime SHIMADA, Shinji TOMITA,
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Abstract(in English) There's a technique called ALU cascading which executes several instructions under data dependency relationship in one clock cycle. Such execution is achieved by concatenating the output of the ALU into the input of the other ALU. To implement this technique to current superscalar processor, we have to prepare instruction scheduler which can wakeup pair of cascaded instructions simultaneously. In this paper, we propose the instruction scheduler which enables ALU cascading. The evaluation result shows that the IPC of SPECint2000 improves by 6.6% in average with 2 level ALU cascading.
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Paper # ICD2007-32
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Conference Date 2007/5/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
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Title (in English) The Dynamic Instruction Scheduler for ALU Cascading
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1st Author's Name Kosuke OGATA
1st Author's Affiliation Graduate School of Informatics, Kyoto University:Graduate School of Law, Kyoto University()
2nd Author's Name Jun YAO
2nd Author's Affiliation Graduate School of Informatics, Kyoto University:Graduate School of Law, Kyoto University
3rd Author's Name Shinobu MIWA
3rd Author's Affiliation Graduate School of Informatics, Kyoto University:Graduate School of Law, Kyoto University
4th Author's Name Hajime SHIMADA
4th Author's Affiliation Graduate School of Informatics, Kyoto University:Graduate School of Law, Kyoto University
5th Author's Name Shinji TOMITA
5th Author's Affiliation Graduate School of Informatics, Kyoto University:Graduate School of Law, Kyoto University
Date 2007-06-01
Paper # ICD2007-32
Volume (vol) vol.107
Number (no) 76
Page pp.pp.-
#Pages 6
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