Presentation 2007-06-01
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design
Hasitha M. WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA,
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Abstract(in English) This paper presents a method to minimize the total energy consumption under time and area constraints, considering interconnection and functional unit (FU) energy. Multiple supply and threshold voltage scheme is used to minimize the static and dynamic energy in the FUs. A genetic-algorithm-based-search method is proposed for the energy consumption minimization problem, so that near-optimal solution can be found in a reasonable time for large-size problems. Interconnection energy reduction is achieved by increasign the sharing of interconnections among FUs. Experimental results show that up to 50% of energy can be saved by our proposed method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) high-level synthesis / low power / interconnection / genetic algorithm
Paper # ICD2007-31
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Committee ICD
Conference Date 2007/5/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design
Sub Title (in English)
Keyword(1) high-level synthesis
Keyword(2) low power
Keyword(3) interconnection
Keyword(4) genetic algorithm
1st Author's Name Hasitha M. WAIDYASOORIYA
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Masanori HARIYAMA
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Michitaka KAMEYAMA
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2007-06-01
Paper # ICD2007-31
Volume (vol) vol.107
Number (no) 76
Page pp.pp.-
#Pages 6
Date of Issue