| Presentation | 2007-06-01 Evaluation of "Write Assurance Buffer" for Dynamic Timing-error Detection HIDETSUGU IRIE, KEN SUGIMOTO, MASAHIRO GOSHIMA, SHUICHI SAKAI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, conventional worst-case logic design is getting unrealistic because of variations in the manufacturing and operational environments. Some techniques to detect run-time timing error have been proposed to attack these problems. In this paper, we perform a circuit-level evaluation of "Write Assurance Buffer(WAB)" which we previously proposed. Assuming next-generation device technology and high speed architecture, the model of the register file was determined and evaluated. HSPICE simulation showed that WAB can operate at 500MHZ-1GHz higher frequency than the register file. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | ICD2007-29 |
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| Committee | ICD |
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| Conference Date | 2007/5/24(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of "Write Assurance Buffer" for Dynamic Timing-error Detection |
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| 1st Author's Name | HIDETSUGU IRIE |
| 1st Author's Affiliation | Japan Science and Technology Agency() |
| 2nd Author's Name | KEN SUGIMOTO |
| 2nd Author's Affiliation | Grad. School of Info. Science and Technology, The University of Tokyo |
| 3rd Author's Name | MASAHIRO GOSHIMA |
| 3rd Author's Affiliation | Grad. School of Info. Science and Technology, The University of Tokyo |
| 4th Author's Name | SHUICHI SAKAI |
| 4th Author's Affiliation | Grad. School of Info. Science and Technology, The University of Tokyo |
| Date | 2007-06-01 |
| Paper # | ICD2007-29 |
| Volume (vol) | vol.107 |
| Number (no) | 76 |
| Page | pp.pp.- |
| #Pages | 6 |
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