Presentation | 2007-06-01 Design Techniques of Wave Pipelines Masa-aki FUKASE, Tomoaki SATO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In order to improve tather complicated design and testing methods of wave-pipelines, our policy is to cover rough tuning as well as fine tuning. This is practically useful for both universal chips and FPGAs. The reconfigurable feature of FPGAs is crucial for quickly corresponding to the drastic change of ubiquitous network environment. In this study, we have focused our attention to three key techniques. The first topic is the development of a CAD tool that dynamically shows a wave map. The second topic is the application of wave-pipelining to wequential circuits. The final topic is a double clocking scheme. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Wave-pipeline / sequential logic / design for testability / processor / chip / CMOS |
Paper # | ICD2007-28 |
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Committee | ICD |
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Conference Date | 2007/5/24(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design Techniques of Wave Pipelines |
Sub Title (in English) | |
Keyword(1) | Wave-pipeline |
Keyword(2) | sequential logic |
Keyword(3) | design for testability |
Keyword(4) | processor |
Keyword(5) | chip |
Keyword(6) | CMOS |
1st Author's Name | Masa-aki FUKASE |
1st Author's Affiliation | Dept. of Electronic and Information Systems Engineering, Hirosaki University() |
2nd Author's Name | Tomoaki SATO |
2nd Author's Affiliation | Computer and Network Systems Center, Hirosaki University |
Date | 2007-06-01 |
Paper # | ICD2007-28 |
Volume (vol) | vol.107 |
Number (no) | 76 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |