Presentation 2007-05-31
A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000
Naomi SEKI, Yohei HASEGAWA, Hideharu AMANO, Naoaki OHKUBO, Seidai TAKEDA, Toshihiro KASHIMA, Toshiaki SHIRAI, Kimiyoshi USAMI, Masaaki KONDO, Hiroshi NAKAMURA,
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Abstract(in English) A novel fine grain power gating technique in a processor is proposed for saving leakage power in the future semiconductor processes. By dividing an execution unit into four small units: multiplier, divider, shifter and others and cut off the power dynamically based on the operation, both dynamic and static power can be reduced. We implemented the chip layout of MIPS R3000 with the proposed mechanism using 90nm CMOS technology, and evaluated area and consuming power. Evaluation results of some benchmark programs for embedded application show that 31% leakage power and 59% dynamic power are reduced in avarage with 34% area overhead.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Dynamic Sleep Control / Power Gating / Leak Power
Paper # ICD2007-25
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Committee ICD
Conference Date 2007/5/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000
Sub Title (in English)
Keyword(1) Dynamic Sleep Control
Keyword(2) Power Gating
Keyword(3) Leak Power
1st Author's Name Naomi SEKI
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Yohei HASEGAWA
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Hideharu AMANO
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
4th Author's Name Naoaki OHKUBO
4th Author's Affiliation Department of Information Science and Engineering, Shibaura Institute of Technology
5th Author's Name Seidai TAKEDA
5th Author's Affiliation Department of Information Science and Engineering, Shibaura Institute of Technology
6th Author's Name Toshihiro KASHIMA
6th Author's Affiliation Department of Information Science and Engineering, Shibaura Institute of Technology
7th Author's Name Toshiaki SHIRAI
7th Author's Affiliation Department of Information Science and Engineering, Shibaura Institute of Technology
8th Author's Name Kimiyoshi USAMI
8th Author's Affiliation Department of Information Science and Engineering, Shibaura Institute of Technology
9th Author's Name Masaaki KONDO
9th Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
10th Author's Name Hiroshi NAKAMURA
10th Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
Date 2007-05-31
Paper # ICD2007-25
Volume (vol) vol.107
Number (no) 76
Page pp.pp.-
#Pages 6
Date of Issue