| Presentation | 2007-05-31 A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption Kiyoshi HAYASE, Yutaka Yoshida, Tatsuya KAMEI, Shinichi SHIBAHARA, Osamu NISHII, Toshihiro HATTORI, Atsushi HASEGAWA, Masashi TAKADA, Naohiko IRIE, Kunio UCHIYAMA, Toshihiko ODAKA, Kiwamu TAKADA, Keiji KIMURA, Hironori KASAHARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | 4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. The 32KB-data cache is built into each processor, and the module to maintain the coherency of the data cache between processors is built into. A low electric power is achieved by frequency control of each processor according to amount of processing and adopting sleep mode that maintains coherency of the data cache between processors. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi processor / individually managed clock frequency / cache coherency / NESI protocol |
| Paper # | ICD2007-22 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/5/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption |
| Sub Title (in English) | |
| Keyword(1) | multi processor |
| Keyword(2) | individually managed clock frequency |
| Keyword(3) | cache coherency |
| Keyword(4) | NESI protocol |
| 1st Author's Name | Kiyoshi HAYASE |
| 1st Author's Affiliation | Renesas Technology Corp.() |
| 2nd Author's Name | Yutaka Yoshida |
| 2nd Author's Affiliation | Renesas Technology Corp. |
| 3rd Author's Name | Tatsuya KAMEI |
| 3rd Author's Affiliation | Renesas Technology Corp. |
| 4th Author's Name | Shinichi SHIBAHARA |
| 4th Author's Affiliation | Renesas Technology Corp. |
| 5th Author's Name | Osamu NISHII |
| 5th Author's Affiliation | Renesas Technology Corp. |
| 6th Author's Name | Toshihiro HATTORI |
| 6th Author's Affiliation | Renesas Technology Corp. |
| 7th Author's Name | Atsushi HASEGAWA |
| 7th Author's Affiliation | Renesas Technology Corp. |
| 8th Author's Name | Masashi TAKADA |
| 8th Author's Affiliation | Hitachi Ltd. |
| 9th Author's Name | Naohiko IRIE |
| 9th Author's Affiliation | Hitachi Ltd. |
| 10th Author's Name | Kunio UCHIYAMA |
| 10th Author's Affiliation | Hitachi Ltd. |
| 11th Author's Name | Toshihiko ODAKA |
| 11th Author's Affiliation | Hitachi Ltd. |
| 12th Author's Name | Kiwamu TAKADA |
| 12th Author's Affiliation | Hitach ULSI Systems Co., Ltd. |
| 13th Author's Name | Keiji KIMURA |
| 13th Author's Affiliation | Waseda University |
| 14th Author's Name | Hironori KASAHARA |
| 14th Author's Affiliation | Waseda University |
| Date | 2007-05-31 |
| Paper # | ICD2007-22 |
| Volume (vol) | vol.107 |
| Number (no) | 76 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |