| Presentation | 2007-05-31 Effect of Data Prefetching on Chip MultiProcessor Naoto FUKUMOTO, Tomonobu MIHARA, Koji INOUE, Kazuaki MURAKAMI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Chip MultiProcessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasing the number of processor cores in a chip dramatically improves the peak performance. However, since the memory bandwidth does not scale with the number of cores, the negative impact of the memory-wall problem becomes more critical. Data prefetching is a well known approach to compensating for the poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed that the processor core in a chip is only one. In CMP chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMPs should be different from that on single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetch operations issued during a program execution. Then, we discuss qualitatively and quantitatively the effect of prefetching to the memory performance. The experimental results show that the negative effect of invalidation of prefetched data is very small. In addition, it is observed that about 5% prefetch operations improve the cache hit rates of other cores. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMP / data prefetching / cache memory |
| Paper # | ICD2007-20 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/5/24(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effect of Data Prefetching on Chip MultiProcessor |
| Sub Title (in English) | |
| Keyword(1) | CMP |
| Keyword(2) | data prefetching |
| Keyword(3) | cache memory |
| 1st Author's Name | Naoto FUKUMOTO |
| 1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Tomonobu MIHARA |
| 2nd Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| 3rd Author's Name | Koji INOUE |
| 3rd Author's Affiliation | Faculty of Information Science and Electrical Engineering, Kyushu University |
| 4th Author's Name | Kazuaki MURAKAMI |
| 4th Author's Affiliation | Faculty of Information Science and Electrical Engineering, Kyushu University |
| Date | 2007-05-31 |
| Paper # | ICD2007-20 |
| Volume (vol) | vol.107 |
| Number (no) | 76 |
| Page | pp.pp.- |
| #Pages | 6 |
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