| Presentation | 2007-05-31 A Study on Control Scheme of Awake Time in Drowsy Caches Ryotaro KOBAYASHI, Hideki TANIGUCHI, Toshio SHIMADA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently static power due to the leakage current has been a major problem as process technology advances. Drowsy Cache is one of the techniques to reduce the leakage power consumed in a cache which contains a large amount of transistors. In this paper, we focus on Drowsy Cache and propose a scheme that controls the interval for which a cache line is kept active in order to achieve the given performance or the given static power. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low-leakage cache / Leakage current / Line control scheme |
| Paper # | ICD2007-18 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/5/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on Control Scheme of Awake Time in Drowsy Caches |
| Sub Title (in English) | |
| Keyword(1) | Low-leakage cache |
| Keyword(2) | Leakage current |
| Keyword(3) | Line control scheme |
| 1st Author's Name | Ryotaro KOBAYASHI |
| 1st Author's Affiliation | Graduate School of Engineering, Nagoya University() |
| 2nd Author's Name | Hideki TANIGUCHI |
| 2nd Author's Affiliation | Graduate School of Engineering, Nagoya University |
| 3rd Author's Name | Toshio SHIMADA |
| 3rd Author's Affiliation | Graduate School of Engineering, Nagoya University |
| Date | 2007-05-31 |
| Paper # | ICD2007-18 |
| Volume (vol) | vol.107 |
| Number (no) | 76 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |