| Presentation | 2007-04-27 Phase Noise and Spurious Level Characteristics in All-Digital PLL Tsuyoshi TERAO, Kiyomichi ARAKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | All-Digital PLL(ADPLL) has been proposed for local oscillators of digital RF transceivers, which are suitable for CMOS single-chip transceivers. In this report, we analyze the phase noise and spurious level of ADPLL. We calculate how much the process variation in inverter chain of Time-to-Digital Converter(TDC) effects on phase noise of ADPLL, and verified with the simulation results. The frequency positions of spurious signals generated by the fractional behavior of PLL are also determined, and the parameters determining the spurious level are enumerated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital RF / PLL / ΣΔ-Modulation / Loop Filter / TDC |
| Paper # | SCE2007-1,MW2007-1 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2007/4/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Phase Noise and Spurious Level Characteristics in All-Digital PLL |
| Sub Title (in English) | |
| Keyword(1) | Digital RF |
| Keyword(2) | PLL |
| Keyword(3) | ΣΔ-Modulation |
| Keyword(4) | Loop Filter |
| Keyword(5) | TDC |
| 1st Author's Name | Tsuyoshi TERAO |
| 1st Author's Affiliation | Graduate School of Science an Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Kiyomichi ARAKI |
| 2nd Author's Affiliation | Graduate School of Science an Engineering, Tokyo Institute of Technology |
| Date | 2007-04-27 |
| Paper # | SCE2007-1,MW2007-1 |
| Volume (vol) | vol.107 |
| Number (no) | 27 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |