Presentation 2007-04-20
A Scheduling Algorithm in High-Level Synthesis for Soft Error Tolerance with Chained Operations
Shintaro IMAMURA, Hideyuki ICHIHARA, Tomoo INOUE,
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Abstract(in English) Soft errors refer to intermittent malfunctions, which are not physical defects. Due to the high speed and low voltage operation of VLSIs, soft errors caused by particle strikes on combinational logics cannot be disregarded, not just on memory elements. According to the model of soft errors presented in, focusing on the observation that a logic chain attenuates the noise caused by a particle strike on the logics, we propose a heuristic algorithm of scheduling in high-lebel synthesis for reducing the sof error rate. Several case studies show that the proposed algorithm can effectively reduce the soft error rate while achieving minimum latencies under resource constraints.
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Keyword(in English) High-level synthesis / soft error / chaining / scheduling
Paper # CPSY2007-2,DC2007-2
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Committee DC
Conference Date 2007/4/13(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Scheduling Algorithm in High-Level Synthesis for Soft Error Tolerance with Chained Operations
Sub Title (in English)
Keyword(1) High-level synthesis
Keyword(2) soft error
Keyword(3) chaining
Keyword(4) scheduling
1st Author's Name Shintaro IMAMURA
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Hideyuki ICHIHARA
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name Tomoo INOUE
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 2007-04-20
Paper # CPSY2007-2,DC2007-2
Volume (vol) vol.107
Number (no) 17
Page pp.pp.-
#Pages 6
Date of Issue