| Presentation | 2007/3/9 Acceleration of Prototyping Design Verification Using Circuit Modification Keita INOUE, Xing WEIJIE, Shinji KIMURA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent SoC (System on Chip) design, more then 60% of design period has been spent by the verification, so we need efficient verification method to reduce the verification time. In the verification, functional simulation is mainly applied, and the acceleration of the simulation by using hardware emulation with FPGA is considered effective. The emulation for large circuits, however, is rather slow, and the speed-up is expected for the reduction of the verification time. In this report, we show an accelerator method based on synchronous pipelining and false-path based combinational circuit delay reduction method. The synchronous pipelining is effective to one-dimensional processing circuits. In the false path-based methods, we focus on the 0&1 skip method where we propagate 0-signal and 1-signal separately. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / false path / Synchronous micro pipeline / Prototyping / Emulation |
| Paper # | CPSY2006-96,DC2006-110 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2007/3/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Acceleration of Prototyping Design Verification Using Circuit Modification |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | false path |
| Keyword(3) | Synchronous micro pipeline |
| Keyword(4) | Prototyping |
| Keyword(5) | Emulation |
| 1st Author's Name | Keita INOUE |
| 1st Author's Affiliation | Graduate School of Information, Production, and Systems, Waseda University() |
| 2nd Author's Name | Xing WEIJIE |
| 2nd Author's Affiliation | Graduate School of Information, Production, and Systems, Waseda University |
| 3rd Author's Name | Shinji KIMURA |
| 3rd Author's Affiliation | Graduate School of Information, Production, and Systems, Waseda University |
| Date | 2007/3/9 |
| Paper # | CPSY2006-96,DC2006-110 |
| Volume (vol) | vol.106 |
| Number (no) | 604 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |