Presentation 2007/3/9
Efficient Translation of Logic Circuits to CNF Formulae with BDD for Acceralating SAT-based Formal Verification
Kazuhiro NAKAMURA, Tomohiro NARUSE, Kazuyoshi TAKAGI, Naofumi TAKAGI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we present a translation framework of circuits to CNF formulae for acceralating SAT-based formal verification. The translation framework consists of three elements, circuit partitioning, construction of BDDs and conversion of BDDs to CNF formulae. We also present a translation method of circuits to CNF formulae based on the translation framework. Experimental results show that the proposed method has effect on the reduction of SAT-solver execution time.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SAT / BDD / CNF formulae / formal verification / logic circuits
Paper # CPSY2006-95,DC2006-109
Date of Issue

Conference Information
Committee DC
Conference Date 2007/3/9(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Efficient Translation of Logic Circuits to CNF Formulae with BDD for Acceralating SAT-based Formal Verification
Sub Title (in English)
Keyword(1) SAT
Keyword(2) BDD
Keyword(3) CNF formulae
Keyword(4) formal verification
Keyword(5) logic circuits
1st Author's Name Kazuhiro NAKAMURA
1st Author's Affiliation Graduate School of Information Science, Nagoya University()
2nd Author's Name Tomohiro NARUSE
2nd Author's Affiliation School of Engineering, Nagoya University
3rd Author's Name Kazuyoshi TAKAGI
3rd Author's Affiliation Graduate School of Information Science, Nagoya University
4th Author's Name Naofumi TAKAGI
4th Author's Affiliation Graduate School of Information Science, Nagoya University
Date 2007/3/9
Paper # CPSY2006-95,DC2006-109
Volume (vol) vol.106
Number (no) 604
Page pp.pp.-
#Pages 6
Date of Issue