Presentation 2007/3/9
A Hardware Design Method Using Semi-Programmable Reconfigurable Processor
Akira YAMAWAKI, Masahiko IWANE,
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Abstract(in English) On a HW/SW co-design system, generating HW-HW and SW-SW interfaces is important to provide fair performance and hardware size. However, it is difficult to provide each process a specific interface circuit. Also, memory access latency becomes larger relative to the execution time reduced. This paper proposes introducing Semi-Programmable ReConfigurable Processor (SPRCP) to a HW/SW co-design system as a frame work of the hardware module. The SPRCP consists of a load/store unit and a hardware unit. The farmer is a tiny processor for memory access and the latter is a reconfigurable hardware unit. The register file is lies between them and provides the hardware unit an easy systematic interface. Instead of hardware unit, the load/store unit performs the flexible memory access and overlaps the memory accesses and hardware execution to hide memory access latency.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) codesign / interface / reconfigurable processor / memory / hardware design
Paper # CPSY2006-89,DC2006-103
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Conference Date 2007/3/9(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hardware Design Method Using Semi-Programmable Reconfigurable Processor
Sub Title (in English)
Keyword(1) codesign
Keyword(2) interface
Keyword(3) reconfigurable processor
Keyword(4) memory
Keyword(5) hardware design
1st Author's Name Akira YAMAWAKI
1st Author's Affiliation Faculty of Engineering, Kyushu Institute of Technology()
2nd Author's Name Masahiko IWANE
2nd Author's Affiliation Faculty of Engineering, Kyushu Institute of Technology
Date 2007/3/9
Paper # CPSY2006-89,DC2006-103
Volume (vol) vol.106
Number (no) 604
Page pp.pp.-
#Pages 6
Date of Issue