Presentation | 2007/3/9 Parallelization with area partitioning for FPGA placement algorithm base on SA Tomohiro OKAJIMA, Yuji ARIUCHI, Morihiro KUGA, Masahiro IIDA, Toshinori SUEYOSHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Placement is one of the most time-consuming processes in automatically logic synthesis and layout for FPGAs. As FPGAs have improved circuit performance, the circuit scale that is implemented by FPGAs becomes larger. Then the computation time devoted to placement has grown dramatically. In this paper, we applied the parallel algorithm that based on area partitioning to FPGA placement using SA on cluster computer. Generally FPGAs have regular structure, therefore, area partitioning technique is effective. Experimental results show that parallelization with area partitioning is effective when the circuit size is large. For large circuits, it achieves nearly linear speed up without significant cost deterioration. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA placement / parallel algorithm / area partitioning / cluster computer |
Paper # | CPSY2006-87,DC2006-101 |
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Committee | DC |
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Conference Date | 2007/3/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Parallelization with area partitioning for FPGA placement algorithm base on SA |
Sub Title (in English) | |
Keyword(1) | FPGA placement |
Keyword(2) | parallel algorithm |
Keyword(3) | area partitioning |
Keyword(4) | cluster computer |
1st Author's Name | Tomohiro OKAJIMA |
1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
2nd Author's Name | Yuji ARIUCHI |
2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
3rd Author's Name | Morihiro KUGA |
3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
4th Author's Name | Masahiro IIDA |
4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
5th Author's Name | Toshinori SUEYOSHI |
5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
Date | 2007/3/9 |
Paper # | CPSY2006-87,DC2006-101 |
Volume (vol) | vol.106 |
Number (no) | 604 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |