| Presentation | 2007/3/8 A Method for Verifying Performance Requirements and Optimizing Communication Scheduling of Network-on-Chip Wataru MURAI, Daisuke HAYASHI, Akio NAKATA, Tomoya KITANI, Keiichi YASUMOTO, Teruo HIGASHINO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a method for verifying performance requirements of Network-on-Chip(NoC) considering dynamic communication behavior of IP cores, and an optimization method of packet scheduling to guarantee performence requirements. In the proposed verification method, a microscopic dynamic behavior of an entire NoC architecture including communication behavior of IP cores is modeled by Time Petri Nets, and then whether given latency/throughput requirements for all communications are satisfied is checked using model checking. In the proposed optimization method, first, time constraints are assigned for each NoC router so that the given latency requirement can be satisfied for each communication flow of an application, and based on that, a TDMA scheduling for each router and each flow is derived according to the static real-time scheduling theory. By iteratively applying the verification method and the refining the TDMA scheduling in a certain policy, a resource-efficient and performance-guaranteed NoC communication scheduling can be explored. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network on Chip / Model Checking / Time Petri Xets / Optimization / Scheduling |
| Paper # | CPSY2006-81,DC2006-95 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2007/3/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method for Verifying Performance Requirements and Optimizing Communication Scheduling of Network-on-Chip |
| Sub Title (in English) | |
| Keyword(1) | Network on Chip |
| Keyword(2) | Model Checking |
| Keyword(3) | Time Petri Xets |
| Keyword(4) | Optimization |
| Keyword(5) | Scheduling |
| 1st Author's Name | Wataru MURAI |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Daisuke HAYASHI |
| 2nd Author's Affiliation | Faculty of Engineering Science, Osaka University |
| 3rd Author's Name | Akio NAKATA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 4th Author's Name | Tomoya KITANI |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Advanced Institute of Science and Technology |
| 5th Author's Name | Keiichi YASUMOTO |
| 5th Author's Affiliation | Graduate School of Information Science, Nara Advanced Institute of Science and Technology |
| 6th Author's Name | Teruo HIGASHINO |
| 6th Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2007/3/8 |
| Paper # | CPSY2006-81,DC2006-95 |
| Volume (vol) | vol.106 |
| Number (no) | 603 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |