Presentation 2007-03-09
Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor
Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa,
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Abstract(in English) In past time, the research that Viterbi decoder is achieved on VLSI was studied, but it was unique research that Viterbi decoder has changed constraint length or any other decode conditions. Using FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device) which are traditional reprogrammable not need to prepare more decoding circuits, but there was a failure that it takes a long time to reconfigure the circuit. In this paper, we used Reconfigurable Processor DAPDNA-II and we had implemented Viterbi decoder among four constraint length from 3 to 6. In this paper, using BER and performed the simulation of changing constraint length. In the result, when the throughput was fixed on 6.40Mbps, and the reconfiguration of circuit was performing frequently, it is compared with constraint length of the best performance, we had confirmed the reduction of power consumption about 40%-80%.
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Keyword(in English) Viterbi decode / Reconfigurable Processor / Software-Defined Radio
Paper # SR2006-90
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Conference Date 2007/3/2(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor
Sub Title (in English)
Keyword(1) Viterbi decode
Keyword(2) Reconfigurable Processor
Keyword(3) Software-Defined Radio
1st Author's Name Yuken Kishimoto
1st Author's Affiliation Faculty of Science and Engineering, Keio University()
2nd Author's Name Shinichiro Haruyama
2nd Author's Affiliation Faculty of Science and Engineering, Keio University
3rd Author's Name Masao Nakagawa
3rd Author's Affiliation Faculty of Science and Engineering, Keio University
Date 2007-03-09
Paper # SR2006-90
Volume (vol) vol.106
Number (no) 558
Page pp.pp.-
#Pages 5
Date of Issue