Presentation 2007-03-06
An Educational Verification System for processors by FPGA
Yuichi NAKAMURA, Chiaki Arao, Kouhei Hosokawa,
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Abstract(in English) This paper describes an educational verification system for processors by FPGA. Generally, since it is difficult to develop the accurate and fast simulator for processors, the software verified by the simulator, may not work on the FPGA or LSI. Then, we proposed the processor verification system by the combined FPGA and PC. The proposed verification system can be controlled by PC and it can display the current status of the processors. We propose the educational verification system for the Z80 compatible processors. The system provides the environments how to develop the control and the display systems on FPGA and PC. The clock accurate and fast, up to 400 KHz, the simulator of the Z80 compatible processor can be developed in 2 days, by using the proposed system. The development of the proposed system would help the understanding of a processor architecture and simulator.
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Keyword(in English) Processor / Simulator / Verification / FPGA
Paper # CAS2006-100,SIP2006-201,CS2006-117
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Conference Information
Committee SIP
Conference Date 2007/2/27(1days)
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Registration To Signal Processing (SIP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Educational Verification System for processors by FPGA
Sub Title (in English)
Keyword(1) Processor
Keyword(2) Simulator
Keyword(3) Verification
Keyword(4) FPGA
1st Author's Name Yuichi NAKAMURA
1st Author's Affiliation Media and Information Research Labs.()
2nd Author's Name Chiaki Arao
2nd Author's Affiliation NEC Software Hokuriku
3rd Author's Name Kouhei Hosokawa
3rd Author's Affiliation Media and Information Research Labs.
Date 2007-03-06
Paper # CAS2006-100,SIP2006-201,CS2006-117
Volume (vol) vol.106
Number (no) 570
Page pp.pp.-
#Pages 2
Date of Issue