Presentation 2007-03-06
Computation reduction in linear transform circuit synthesis using genetic algorithm
Mai SUZUKI, Takao SASAKI, Hisamichi TOYOSHIMA,
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Abstract(in English) A linear transform circuit is often used in various transform such as DCT and DFT. In realizing in hardware, it is important to reduce delay time and circuit area. By replacing each constant multiplier with shifts and additions, and sharing them, the circuit area can be reduced. However, in the solution using a combinatorial optimization, the problem occurs that the computation and the optimality deteriorate as the size of the coefficient matrix grows. In this study, we propose the method of the computation reduction by partitioning the coefficient matrix and synthesizing each sub-matrix optimally. Furthermore, reducing the search space efficiently, the relation between the optimality and the computation of the linear transform circuit synthesis is verified.
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Keyword(in English) genetic algorithm / optimization / linear transform circuit / computation reduction
Paper # CAS2006-97,SIP2006-198,CS2006-114
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Committee SIP
Conference Date 2007/2/27(1days)
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Registration To Signal Processing (SIP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Computation reduction in linear transform circuit synthesis using genetic algorithm
Sub Title (in English)
Keyword(1) genetic algorithm
Keyword(2) optimization
Keyword(3) linear transform circuit
Keyword(4) computation reduction
1st Author's Name Mai SUZUKI
1st Author's Affiliation Faculty of Engineering, Kanagawa University()
2nd Author's Name Takao SASAKI
2nd Author's Affiliation Faculty of Engineering, Kanagawa University
3rd Author's Name Hisamichi TOYOSHIMA
3rd Author's Affiliation Faculty of Engineering, Kanagawa University
Date 2007-03-06
Paper # CAS2006-97,SIP2006-198,CS2006-114
Volume (vol) vol.106
Number (no) 570
Page pp.pp.-
#Pages 3
Date of Issue