Presentation 2007-03-06
A Research on Fast of Analytical Placement
Naoto FUNATSU, Takumi KURAHARA, Yasuhiro TAKASHIMA,
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Abstract(in English) In recent years, the total wirelength is the important factor which determines a performance in an integrated circuit design, and the analytical placement suitable for wirelength optimization attracts attention. Although the analytical placement is fast, a circuit becomes still larger-scale and its execution time poses a problem. Since the wirelength evaluation is dominant in the execution time, we propose a bundle technique of nets to shorten the time. For analytical placement, various wirelentgth estimations has been proposed. In this paper, we note two approximations, such as logarithm-sum-exponential (LSE) and CHKS. We show the effect of our bundle method for them empirically.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Analytical placement / Bundle technique / LSE / CHKS
Paper # CAS2006-96,SIP2006-197,CS2006-113
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Committee SIP
Conference Date 2007/2/27(1days)
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Registration To Signal Processing (SIP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Research on Fast of Analytical Placement
Sub Title (in English)
Keyword(1) Analytical placement
Keyword(2) Bundle technique
Keyword(3) LSE
Keyword(4) CHKS
1st Author's Name Naoto FUNATSU
1st Author's Affiliation The University of Kitakyushu Faculty of Environmental Engineering Department of Information and Media Sciences()
2nd Author's Name Takumi KURAHARA
2nd Author's Affiliation The University of Kitakyushu Faculty of Environmental Engineering Department of Information and Media Sciences
3rd Author's Name Yasuhiro TAKASHIMA
3rd Author's Affiliation The University of Kitakyushu Faculty of Environmental Engineering Department of Information and Media Sciences
Date 2007-03-06
Paper # CAS2006-96,SIP2006-197,CS2006-113
Volume (vol) vol.106
Number (no) 570
Page pp.pp.-
#Pages 4
Date of Issue