Presentation 2007-03-05
Design of a 10-bit, 40MSample/s Current-Steering D/A Converter for WLAN Applications
Shinji OTAKI, Takeshi UENO, Tetsuro ITAKURA,
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Abstract(in English) In an advanced CMOS technology, the supply voltage has been decreased and digital circuits should operate at 1.2V supply voltage in 90nm CMOS process. In wireless communication, since D/A converter is often integrated with digital baseband circuits, it is desirable to operate at the same voltage as digital circuits. In this article, we propose a current-steering D/A converter using folded cascode architecture, which operates at 1.2V supply voltage and achieves 1.0V_ output swing. For WLAN applications, sampling rate is 40MSPS and resolution is 10 bit. Simulation results show that SFDR is 67dB at 1MHz input frequency. Folded cascode architecture is effective to design D/A converters that operate at low supply voltage and achieve high output swing.
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Keyword(in English) D/A converter / low supply voltage / folded cascode
Paper # CAS2006-87,SIP2006-188,CS2006-104
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Committee CS
Conference Date 2007/2/26(1days)
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Registration To Communication Systems (CS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of a 10-bit, 40MSample/s Current-Steering D/A Converter for WLAN Applications
Sub Title (in English)
Keyword(1) D/A converter
Keyword(2) low supply voltage
Keyword(3) folded cascode
1st Author's Name Shinji OTAKI
1st Author's Affiliation Mobile Communication Laboratory, Corporate Research & Development Center, Toshiba Corporation()
2nd Author's Name Takeshi UENO
2nd Author's Affiliation Mobile Communication Laboratory, Corporate Research & Development Center, Toshiba Corporation
3rd Author's Name Tetsuro ITAKURA
3rd Author's Affiliation Mobile Communication Laboratory, Corporate Research & Development Center, Toshiba Corporation
Date 2007-03-05
Paper # CAS2006-87,SIP2006-188,CS2006-104
Volume (vol) vol.106
Number (no) 571
Page pp.pp.-
#Pages 5
Date of Issue