Presentation 2007-03-09
Statictical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations
Katsumi HOMMA, Izumi NITTA, Toshiyuki SHIBUYA,
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Abstract(in English) Statistical Timing Analysis(SSTA) is a method that calculates circuit delay statistically with process variations. In SSTA, the delay variations are divided into intra-die and inter die variations. Intra-die variations are independent for each cells and lines in a chip. Inter-chip variations area governed by one variation on a chip. In this paper, we propose a new method of computing whole chip delay distribution considering inter and intra-chip variations in path-based SSTA. In practical LSI data experiments, it is confirmed that the propose method is more accurate than previous methods.
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Keyword(in English) Statistical Static Timing Analysis / Intra-die variations / Inter-die variations / Path-based Analysis
Paper # VLD2006-156,ICD2006-247
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Conference Date 2007/3/2(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Statictical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations
Sub Title (in English)
Keyword(1) Statistical Static Timing Analysis
Keyword(2) Intra-die variations
Keyword(3) Inter-die variations
Keyword(4) Path-based Analysis
1st Author's Name Katsumi HOMMA
1st Author's Affiliation FUJITSU LABORATORIES LTD.()
2nd Author's Name Izumi NITTA
2nd Author's Affiliation FUJITSU LABORATORIES LTD.
3rd Author's Name Toshiyuki SHIBUYA
3rd Author's Affiliation FUJITSU LABORATORIES LTD.
Date 2007-03-09
Paper # VLD2006-156,ICD2006-247
Volume (vol) vol.106
Number (no) 552
Page pp.pp.-
#Pages 6
Date of Issue