| Presentation | 2007-03-09 Analysis for factors that affect power dissipation for Multiplier applying Run Time Power Gating Seidai TAKEDA, Toshihiro KASHIMA, Toshiaki SHIRAI, Naoaki OHKUBO, Kimiyoshi USAMI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes major factor that affect power dissipation for dynamic sleep control. We analyzed factors through power analysis for a 32bit multiplier applying Run Time Power Gating(RTPG). This multiplier has a scheme to dynamically reduce the leakage power according to bit size of multiplied values. If one or both multiplied values have less than 16bit value, power gating is dynamically applied to the part of logic gates that need not to calculate output values. We design and implement this multiplier using ASPLA 90nm technology and analyze the leakage power. Experimental results show that this scheme enables to reduce the average leakage power of multiplier in circuit by up to 46% putting a part of multiplier into sleep at 85℃, however, It required approximately 20ns from he sleep start to the point at which leakage current in the multiplier circuit begins to reduce. Also it required approximately1.2us to achieve maximum leakage power reduction. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MTCMOS circuits / Dynamic Sleep Control / Active Leakage Power / Power Dissipation |
| Paper # | VLD2006-154,ICD2006-245 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2007/3/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis for factors that affect power dissipation for Multiplier applying Run Time Power Gating |
| Sub Title (in English) | |
| Keyword(1) | MTCMOS circuits |
| Keyword(2) | Dynamic Sleep Control |
| Keyword(3) | Active Leakage Power |
| Keyword(4) | Power Dissipation |
| 1st Author's Name | Seidai TAKEDA |
| 1st Author's Affiliation | Graduate School of Engineering, Shibaura Institute of Technology() |
| 2nd Author's Name | Toshihiro KASHIMA |
| 2nd Author's Affiliation | Graduate School of Engineering, Shibaura Institute of Technology |
| 3rd Author's Name | Toshiaki SHIRAI |
| 3rd Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
| 4th Author's Name | Naoaki OHKUBO |
| 4th Author's Affiliation | Graduate School of Engineering, Shibaura Institute of Technology |
| 5th Author's Name | Kimiyoshi USAMI |
| 5th Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
| Date | 2007-03-09 |
| Paper # | VLD2006-154,ICD2006-245 |
| Volume (vol) | vol.106 |
| Number (no) | 552 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |