Presentation 2007-03-09
Design Method of High Density System LSI with Three-Dimensional Transistor(FinFET) : Reduction of Pattern Area
Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) New design method of system LSI with FinFET has been developed. Ushing planar+FinFET architecture the pttern area of system LSI designed by cell library can be reduced to about 30% compared with the conventional planar case. New design method is a promising candidate for realizing future high performance, high-density system LSI.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) system LSI / FinFET / channel width / sidewall channel width / cell library / TIS
Paper # VLD2006-149,ICD2006-240
Date of Issue

Conference Information
Committee ICD
Conference Date 2007/3/2(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design Method of High Density System LSI with Three-Dimensional Transistor(FinFET) : Reduction of Pattern Area
Sub Title (in English)
Keyword(1) system LSI
Keyword(2) FinFET
Keyword(3) channel width
Keyword(4) sidewall channel width
Keyword(5) cell library
Keyword(6) TIS
1st Author's Name Shigeyoshi Watanabe
1st Author's Affiliation Department of Information Science, Shonan Institute of Technology()
2nd Author's Name Keisuke Okamoto
2nd Author's Affiliation Department of Information Science, Shonan Institute of Technology
3rd Author's Name Makoto Oya
3rd Author's Affiliation Department of Information Science, Shonan Institute of Technology
Date 2007-03-09
Paper # VLD2006-149,ICD2006-240
Volume (vol) vol.106
Number (no) 552
Page pp.pp.-
#Pages 6
Date of Issue